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Annonce

6 janvier 2017

CEA-Leti: Postdoctoral Position in High Performance Hardware Architectures for Error Correction Coding


Catégorie : Post-doctorant


CEA-Leti: A postdoctoral position is open in the area of coding theory, focused on the design and implementation of advanced error correction techniques, capable of meeting the most stringent requirements, in terms of area, power, latency, and throughput.

 

Context of the Position

The CEA-Leti, one of the three advanced-research institutes within CEA Tech, is focused on creating value and innovation through technology transfer to its industrial partners. It specializes in nanotechnologies and their applications, from wireless devices and systems, to biology, healthcare and photonics. With a staff of more than 1,900, Leti is based in Grenoble, France, and has offices in Silicon Valley, California, and Tokyo.

Located in Grenoble at the heart of the MINATEC Campus, the wireless broadband systems laboratory (LSHD) is conducting cutting-edge research in wireless communications for broadband and 5G systems, including advanced channel coding and modulation, transceiver design, access control protocols, and radio and network resource management. Its activities cover a large spectrum, from the specification, simulation and characterization, to the design of both SW and HW components for wireless communications.

As part of these activities, a postdoctoral position is open in the area of coding theory, focused on the design and implementation of advanced error correction techniques, capable of meeting the most stringent requirements, in terms of area, power, latency, and throughput. Two main applications may be considered: massive data rate wireless communications and error correcting code non-volatile memories. Envisaged solutions depend on the specific requirements of each of the considered applications, and thus rely on different families of error correcting codes, including LDPC codes and algebraic linear block codes (Reed-Solomon, BCH, Reed-Muller).

Description of the Work

Depending on the considered application, the main objective is to investigate the design of novel low cost and low latency decoding algorithms and corresponding hardware architectures, for either LDPC or algebraic linear block codes.

The main tasks are summarized as follows:

Applicant Profile

Contact Details

Applications should be sent by email to Valentin Savin (valentin.savin@cea.fr) and Dimitri Kténas (dimitri.ktenas@cea.fr), including:

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