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Annonce

11 avril 2018

Hardware architecture design for next-generation Tb/s turbo codes


Catégorie : Post-doctorant


Duration: 12 months (can be probably extended), to start as soon as possible.

Workplace: IMT Atlantique/Electronics Department, Lab-STICC laboratory/IAS Team, Technopole Brest Iroise – CS 83818 – 29238 Brest – France

Complete description of the position:
https://mintel.imt.fr/archive/rh_offres_emploi/Postdoc_EPIC_IMTAtlantique_fr.pdf

Design space exploration and proposal of novel hardware architecture templates able to achieve or approach Tb/s decoding throughputs of next-generation turbo codes. Various parallelism techniques, logic design approaches and memory organization should be explored and devised. Furthermore, the proposed architectural templates should be refined and optimized at lower design levels.

 

Context

This PostDoc position is proposed in the framework of the ongoing H2020 European project EPIC (Enabling Practical Wireless Tb/s Communications with Next Generation Channel Coding, Sep. 2017 -Aug.2020). EPIC aims to develop a new generation of Forward-Error-Correction (FEC) codes in a manner that will serve as a fundamental enabler of practicable beyond 5G wireless Tb/s solutions. Such throughput corresponds to a 10x–100x improvement over state of the art. The EPIC consortium consists of 8 partners from 7 different countries.

Due to the high expertise of IMT Atlantique in designing turbo and related codes, our research team is in charge of the design of turbo-like codes for EPIC. The research activity of the Electronics department of IMT Atlantique is mainly dedicated to the joint design of algorithms and hardware architectures (Algorithm-Silicon Interaction) for digital communication applications. Since the invention of turbo codes in the early nineties, this research team has been internationally recognized for its expertise in channel coding and iterative processing and has designed turbo codes for several 3GPP and DVB standards. The scientific work of the team has already been awarded several national and international prizes, including the 2003 IEEE Richard W. Hamming Medal, the 2005 Marconi Prize or the 2009 IEEE/SEE Glavieux Prize. The team has been recently involved in the design of new FEC codes (turbo and turbo-like codes) for 5G within the H2020 project FANTASTIC-5G (Flexible Air iNTerfAce for Scalable service delivery wiThin wIreless Communication networks of the 5th Generation) and is currently participating in the 5G standardization in 3GPP RAN1 NR (New Radio) activities.

Description and objectives

Efficiently achieving ultra-high throughput (up to and exceeding Tb/s) for turbo codes is very challenging, since turbo codes are inherently serial at the component decoder level (Soft-In Soft-Out decoders). This target entails constraints on the turbo encoder/decoder such as latency and energy efficiency. The following table presents various recent turbo decoder implementations that represent the state of the art options. 

 

Code

 

Ref.

 

Code

 

length

 

Rate

 

support

 

Process

 

Nm

 

Area

 

mm2

 

Freq

 

MHz

 

Throughput

 

Gb/s

 

Area eff.

 

Gb/s/mm2

 

Energy eff.

 

pJ/bit

 

Power dens.

 

W/mm2

Turbo

[1]

18432

LTE

45

2.00

600

1.67

0.83

1500

1.25

Turbo

[2]

18432

LTE

90

19.7

625

2.27-3.3

0.12-0.17

637-438

0.073

Turbo

[3,4]

18432

LTE

65

109

410

15.8

0.145

608

0.09

Additional application-dependent constraints such as code flexibility and error rate performance should also be met. Addressing all of these constraints requires the exploration of code design, decoding algorithms and highly parallel architecture templates. 

In this context, several new ideas are being investigated to design ultra-high throughput classical and flexible-degree convolutional turbo codes. The initial estimations and performance results are very promising. Furthermore, a comprehensive design space and state-of-the-art analysis has been conducted. While pursuing these studies at the algorithm level, we plan to start soon a dedicated design space exploration of the channel decoder in order to propose novel hardware architecture templates able to achieve or approach Tb/s decoding throughputs. This constitutes the main objective of the proposed PostDoC position. Various parallelism techniques, logic design approaches and memory organization should be explored and devised. Furthermore, the proposed architectural templates should be refined and optimized at lower design levels.

Requirements and skills

Application

Qualified candidates are requested to submit their application including a detailed CV and a cover letter by email to the following contact persons:

References

[1] G. Wang, H. Shen, Y. Sun; J. R. Cavallaro, A. Vosoughi; Y. Guo, “Parallel interleaver design for a high throughput HSPA+/LTE multi-standard turbo decoder”, IEEE Transactions on Circuits and Systems, vol. 61, no. 5, pp. 1376 – 1389, May 2014.

[2] R. Shrestha and R. P. Paily, “High-throughput turbo decoder with parallel architecture for LTE wireless communication standards,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 9, pp. 2699-2710, Sept. 2014.

[3] R.G. Maunder, “A fully-parallel turbo decoding algorithm,” IEEE Transactions on Communications, vol. 63, no. 8, pp. 2762-2775, Aug. 2015.

[4] Li, L. Xiang, T. Chen, R. G. Maunder, B. M. Al-Hashimi and L. Hanzo, “VLSI Implementation of Fully Parallel LTE Turbo Decoders”, IEEE Access, vol. 4, pp. 323-346, 2016.

[5] C. Berrou, A. Glavieux and P. Thitimajshima, "Near Shannon limit error-correcting coding and decoding: turbo-codes", IEEE ICC '93, Geneva, 1993, pp. 1064-1070.

 

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