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Architectures de Codes Correcteurs d'Erreurs

Date : 4-11-2014
Lieu : Télécom Bretagne

Thèmes scientifiques :
  • D - Télécommunications : compression, protection, transmission

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15 personnes membres du GdR ISIS, et 25 personnes non membres du GdR, sont inscrits à cette réunion.

Capacité de la salle : 40 personnes.


Journée inter-GDR SoCSiP, ISIS : Architectures de Codes Correcteurs d'Erreurs.

4 novembre 2014, salle B007, Télécom Bretagne, BREST


« Architecture de codes correcteurs d’erreurs »

Journée inter GDR ISIS et SoCSiP

4 novembre 2014, salle B007, Télécom Bretagne, BREST


9h15 : accueil

9h45-10h15 : Stefan Weithoffer / Norbert Wehn (Technische Universität Kaiserslautern), Fully LTE-A compliant Turbo Decoder for Base Station Applications

10h15-10h45 : Li Meng (IMEC), ASIP LDPC for 802.11ad or ac standards.

10h45-11h15 : Benoît Parrein (Univ-Nantes), The Mojette Erasure Code

11h15-11h45 : Cafe Break

11h45:12h15 : David Declercq (ENSEA, Cergy Pontoise), Decoders LDPC FAID.

12h15-12h45 : Camille Leroux (IPB/ENSEIRB-MATMECA), Architecture of polar code decoder.

12h45-14h : Lunch

14h-14h30 : Valentin Savin (CEA LETI), Cost efficient FPGA implementations of Min-Sum and Self-Corrected-Min-Sum decoders.

14h30-15h : Philipp Schläfer / Norbert Wehn (Technische Universität Kaiserslautern), 100 Giga bits LDPC code

15h-15h30 : Charbel ABDEL NOUR (Télécom Bretagne), Title to be defined

15h30-15h50 : Cafe Break

15h50-16h20 : Emmanuel Boutillon (Lab-STICC/UBS), A Survey on Bit Flipping Algorithm

16h20-16h50 : Stefan Scholl / Norbert Wehn (Technische Universität Kaiserslautern), A High Speed Soft-RS Decoder

16h50 : Final discussion

Organisation pratique :

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Résumés des contributions

Fully LTE-A compliant Turbo Decoder for Base Station Applications

Stefan Weithoffer / Norbert When (Technische Universität Kaiserslautern

Designing Turbo decoders for the latest LTE standard is a challenging task. We present a 1Gbit/s fully LTE-A compliant Turbo Decoder performing 14 half-iteration. Transport block CRCs are managed and a new latency reduced on the fly CRC calculation is proposed.

ASIP LDPC for 802.11ad or ac standards

Li Meng (IMEC)

The design of multi-Gbps LDPC decoder has become a hot topic in the recent years as the demand of the evaluation to 4G or even 5G network.  IMEC designed a LDPC decoder processor. The ASIP core is targeting high throughput and it can be configured for the 802.11ad and the 802.11ac standards at the moment and is easy to be configured for the other standards. 

The Mojette Erasure Code

Benoît Parrein (Univ-Nantes)

For twenty years, we developed at University of Nantes (IRCCyN lab) new algorithms and software for erasure coding based on discrete geometry and Radon transforms. Today, the solution is mature and allows incredible throughputs nearly close to the memcopy instruction. A comparison to Jerasure and Intel ISA libraries that implement optimized Reed-Solomon codes will be provided. An example of a complete integration to a scale-out NAS file system will conclude the talk.

Decoders LDPC FAID

David Declercq (ETIS, ENSEA)

Architecture of polar code decoder


Polar coding has been recently proposed as a solution to achieve the capacity of binary input symetric memoryless channels. The inclusion of polar codes in future telecommunication standards highly depends on the efficiency of the hardware polar decoders. This presentation provides an overview of existing architectural solutions aiming at a more efficient implementation of the Successive Cancellation decoder. After a brief presentation of the SC decoding algorithm, we will highlight the different challenges of SC decoding implementation and present different architectural approaches that improve the efficiency of polar decoders.

Cost efficient FPGA implementations of Min-Sum  and Self-Corrected-Min-Sum decoders

Valentin Savin (CEA LETI)

We present memory efficient FPGA implementations for layered quasi-cyclic (QC) LDPC decoders, based on the Self-Corrected Min-Sum (SCMS) algorithm. We address the problem of high memory overhead required by layered SCMS based decoders compared to conventional Min-Sum (MS), by proposing two improvements. These require changes in the flow/rule of the conventional SCMS algorithm, in order to avoid storing the signs and the erasure bits of the variable node messages. FPGA implementation results for WiMAX (1152, 2304) code show that the proposed architecture has a resource utilization with 17% less with respect to the one implementing conventional SCMS. Furthermore, it presents a similar cost to conventional MS, while having a 0.5 dB better error correction capability.

100 Giga bits LDPC code

Philipp Schläfer / Norbert Wehn (Technische Universität Kaiserslautern)

New standards have ever increasing data rates which are challenging to fulfil with state-of-the-art architectures. We present an efficient architecture optimised for very high throughput while maintaining good communications performance. At the same time we propose ways for increased energy efficiency in LDPC decoding.

Low-Complexity LDPC-coded Iterative MIMO Receiver Based on Belief Propagation algorithm for Detection

Charbel ABDEL NOUR (Lab-STICC/Télécom Bretagne)

A low-complexity Multiple Input Multiple Output receiver based on Belief Propagation (MIMO-BP) detector associated with a Non-Binary Low-Density Parity-Check (NB-LDPC) decoder is proposed in this talk. Such detection and decoding algorithms are represented thanks to a larger Joint Factor Graph (JFG). Shuffle schedule is also applied to efficiently exchange information between the detector and the decoder. Actions are undertaken at the detector, decoder and the iterative receiver levels in order to reduce overall computational complexity. An important reduction in terms of operations per iteration is obtained with a negligible performance penalty. Then, EXtrinsic Information Transfer (EXIT) charts are used to find a schedule in terms of number of iterations to be performed for which the proposed receiver achieves similar performance than a full-complexity iterative MIMO receiver.

A Survey on Bit Flipping Algorithm

Emmanuel Boutillon (Lab-STICC/UBS)

In this presentation, we will do a sort review on “single bit message”, with a focus on gradient bit flipping algorithm. We will show that this type of decoding algorithm can give performance close to the believe propagation algorithm with low hardware complexity.

A High Speed Soft-RS Decoder

Stefan Scholl / Norbert Wehn (Technische Universität Kaiserslautern)

Two ways to improve the error correction performance of today's channel coding systems are shown. First, a hardware architecture for soft decision decoding of Reed-Solomon codes is presented based on a information set decoding heuristic, that provides large gain in SNR at moderate complexity. Second, we present an efficient approach based on integer programming to perform exact ML decoding simulations.